The present disclosure is related to the following concurrently filed applications, all of which are to be assigned to Toshiba-Infineon and all of which are hereby incorporated by reference in their entirety into the present disclosure:
xe2x80x9c2T2C Signal Margin Test Mode Using Resistive Elementxe2x80x9d to Michael Jacob et al., attorney reference number FP1783; xe2x80x9c2T2C Signal Margin Test Mode Using Different Pre-Charge Levels for BL and /BLxe2x80x9d to Michael Jacob et al., attorney reference number FP 1806; and xe2x80x9c2T2C Signal Margin Test Mode Using a Defined Charge Exchange Between BL and /BLxe2x80x9d to Hans-Oliver Joachim et al., attorney reference number FP1807.
The present invention relates to the implementation of circuits for testing signal margin in memory cells operating in a 2T2C configuration.
In semiconductor memories, reliability issues have become more complicated with increasing memory sizes, smaller feature sizes and lower operating voltages. It has become more important to understand the cell signal sensing operation, the signal of memory cells and the limiting factors. One particularly important characteristic in reliability determinations of semiconductor memories is the signal margin. In a 2T2C memory cell configuration, the signal margin is a measure of the zero-versus-one signal measured by the sense amplifier. It is particularly useful to be able to measure the signal margin at product level. The results of product-level signal-margin tests can be used to optimize reliability and as well as the sense amplifier design and the bit line architecture to optimize dynamic memory cell readout. Moreover, a product level test sequence for signal margin can help ensure full product functionality over the entire component lifetime taking all aging effects into account.
Among the more recent semiconductor memories, Ferroelectric Random Access Memories (FeRAMs) have attracted much attention due to their low-voltage and high-speed operation in addition to their non-volatility. FIG. 1 shows a typical prior art FeRAM memory cell in a 2T2C configuration. The 2T2C configuration utilizes two transistors and two capacitors per bit. The 2T2C configuration is beneficial because it allows for noise cancellation between the transistors. Two storage capacitors (Cferro) are connected to a common plate line (PL) on one side and to a pair of bit lines (BL, /BL) on the other side via two select transistors (TS). The two transistors are selected simultaneously by a common word line (WL). A dedicated bit line capacitance (CBL) is connected to each bit line. This bit line capacitance is required for the read operation of the memory cell. The differential read signal on the bit line pair is evaluated in a connected sense amplifier. The polarization is always maintained in directly opposed states in the two storage capacitors of one 2T2C memory configuration.
The signals on the bit lines during a read access are shown in FIG. 4. FIG. 4 of the present disclosure is a plot of the read signals on BL /BL vs. time. In these plots, one of the lines represents the read signal on BL and one represents the read signal on /BL. Which signal is represented by which of the lines depends on whether the read signal on DL or the read signal on /BL is larger. First, both bit lines BL and /BL are pre-charged to the same level (e.g. ov in the figure). At time t0 the plate is activated and a read signal appears on the bit lines according to the capacitance ratio Cferro/CBL. The effective capacitance of a ferroelectric capacitor depends on its polarization state prior to the read operation. At time t1 the full read signals are developed on the two bit lines. At t2 the sense amplifier is activated and the bit line signals are boosted to the full bit line voltages. At t3 the sense amplifier is deactivated and the access cycle ends at t4.
A good solution for determining signal margin in FeRAM memory cells utilizing a single transistor and capacitor (1T1C) is to sweep the reference bit line voltage. A prior art method for determining signal margin in 2T2C FeRAM memory cells is to shift the bit line level by capacitor coupling. However, this method is unsatisfactory because it requires an additional capacitor.
It would therefore be desirable to provide a circuit with a test mode section for facilitating a worst case product test sequence for signal margin. It would also be desirable to design such a circuit for use with semiconductor memories in a 2T2C configuration without requiring additional capacitors in the circuit.
The present invention provides a test mode section for facilitating a worst case product test sequence for signal margin to ensure full product functionality over the entire component lifetime taking all aging effects into account. The invention works well with semiconductor memories having a 2T2C configuration.
A first aspect of the present invention proposes in general terms a semiconductor memory test mode configuration includes a first capacitor for storing digital data. The first capacitor connects a cell plate line to a first bit line through a first select transistor. The first select transistor is activated through a connection to a word line. A second capacitor for storing digital data connects the cell plate line to a second bit line through a second select transistor. The second select transistor is also activated through a connection to the word line. A sense amplifier is connected to the first and second bit lines for measuring a differential read signal on the first and second bit lines. A constant current mover, for example a constant current sink or source, is connected to the first bit line through a third transistor for changing the amount of charge on the first bit line when the third transistor is turned on to reduce the differential read signal.
Another aspect of the present invention includes a method for testing a semiconductor memory comprising the steps of; pre-charging first and second bit lines; activating a cell plate line to produce a read signal on the first and second bit lines representing digital data stored by a pair of capacitors connected to the cell plate line through first and second transistors; activating a third transistor connected to the first bit line for a time interval to change the amount of charge on the first bit line by moving charge through a constant current mover connected through the third transistor to the first bit line; activating a sense amplifier connected to the first and second bit lines thereby boosting read signals on the first and second bit lines; and determining a reduced differential read signal on the first and second bit lines due to the changed amount of charge on the first bit line.